The present invention relates to a method and apparatus for testing integrated circuit packages and, in particular, the in situ testing of ball grid array integrated circuits.
While integrated circuit fabrication technology has advanced to allow the fabrication of integrated circuits containing progressively larger numbers of circuit elements and more complex circuits in a given package, the increased density of circuits in a package has resulted in problems in heat dissipation, high speed signal integrity and space for signal input/output connections. Large scale integrated circuits, for example, have traditionally provided input/output pins around the circumference of the package to provide power to the circuits therein and to connect signals into and out of the circuits. The pins in turn are connected, typically by soldering, to pads or lands on a circuit board, which is often multi-layered to provide a greater number of signal leads and connections to the pins of the integrated circuit package. Limitations on the minimum size and spacing of the input/output pins, and of the pads and leads of the circuit board, however, limit the number of available input/output connections to the circuits in the package. As a result, it is often difficult to provide a sufficient number of input/output connections just for the required power and input/output signals, and it is even more difficult, or impossible, to provide a sufficient number of input/output connections for desirable test/debugging signals.
Ball Grid Array (BGA) technology provides a solution to many of these problems in integrated circuit packing by providing significantly improved thermal dissipation, increased package input/output pin counts and improved high speed signal integrity. BGA packaging does not use input/output pins located around the periphery of the package for signal and power input/output connections, but instead provides a grid array of connection points on the xe2x80x9cbottomxe2x80x9d of the package, that is, the side of the package against the circuit board the package is mounted on, that contact a corresponding grid array of pads or lands on the circuit board. Electrical connections between the grid array of contact points on the package and the pads of the circuit board are made by means of xe2x80x9cballsxe2x80x9d of solder on the package contact point, resulting in the term xe2x80x9cball grid arrayxe2x80x9d. It will be apparent that by using a significant portion of the surface area of the bottom face of the package for a grid array of input/output connections, BGA technology thereby allows a significantly increased number of package input/output connections for signal and power connections and for in-circuit connections for testing and debugging of the circuitry.
BGA technology, however, results in a further problem in that a BGA package does not have accessible package pins to which pin clips or substitution clips may be connected to perform testing and debugging operations. While some test connections may be made by means of traces to the pads of the printed circuit board that a BGA package is mounted onto, it is not possible as a practical matter to provide a sufficient number of test pads on the printed circuit board because of space limitations in routing traces to and from the pads. That is, it is necessary to maintain required minimum widths of and spacings between the pads and leads or traces of the circuit board so that, as discussed in the following description of the invention, the number of traces that may be routed between the pads, and in particular to and from the pads in the inner regions of the grid array of contact points, is limited. This problem is not relieved but is in fact compounded by the use of multi-layer circuit boards to provide space for additional traces on the inner and bottom layers of the circuit because the routing of traces from one layer to another requires the use of vias, that is, conductive paths between the layers. As a consequence, each via requires space on each layer of the circuit board that the via penetrates, in the same manner as a pad, thereby reducing the space available for traces on the printed circuit board in the same manner as illustrated in FIG. 1A. The problem is further compounded in multi-layer circuit boards of the prior art because, as illustrated in FIG. 1B, each via is routed through a via pad on each layer the via penetrates and each via pad is connected directly only to the via. As such, each via must be connected to, for example, a pad, by means of an additional trace between the via pad and the pad, thereby occupying even more space on the circuit board. As a result, the ability to perform in-circuit testing and debugging in both the research and development phase and in the production of circuits packaged using BGA technology is severely limited.
Other problems of the BGA technology of the prior art also include, for example, the requirement to provide and carefully control the standoff height between a BGA package and the printed circuit board the package is mounted onto in order to insure the formation of solder xe2x80x9cballsxe2x80x9d of the correct size and shape. Yet another problem of the BGA technology of the prior art is that it is difficult to correct or resolder a faulty connection between a BGA package and the circuit board it is mounted on as the xe2x80x9cballsxe2x80x9d forming the electrical connections are not accessible. It is thereby necessary to remove the BGA package from the circuit board and completely resolder the BGA package to the circuit board in order to correct a faulty joint, with a consequent high risk of damage to either or both of the BGA package or the printed circuit board.
The present invention provides a solution to these and other problems of the prior art.
The present invention is directed to an improved ball grid technology circuit assembly providing enhanced connections between the circuits within a ball grid array circuit package and, for example, test probe connections for testing and debugging of the ball grid array circuits. The ball grid array circuit package contains integrated circuits and includes, on a mounting face of the ball grid array circuit package, a ball grid array of ball pads forming electrical connections to the integrated circuits in the ball grid array circuit package. The circuit package further includes a printed circuit board for mounting the ball grid array circuit package and providing electrical connections to the ball pads of the ball grid array circuit package wherein the ball grid array circuit package is mounted to the printed circuit board with the mounting face of the ball grid array circuit package mating with an upper face of the printed circuit board.
According to the present invention, the printed circuit board further includes a via array of vias wherein each via extends from the upper face of the printed circuit board to a lower face of the printed circuit board, each via corresponds to and is co-located with a ball pad of the ball grid array, and each via contacts the corresponding ball pad of the ball grid array to provide a conductive path between the corresponding ball pad and the lower end of the via at the lower face of the printed circuit board to provide electrical access to the corresponding ball pad of the ball grid array of the ball grid array circuit package.
In a presently preferred embodiment of the invention, the vias have diameters less than or equal to 0.010 inch. In addition, standoffs may be located between the mounting face of the ball grid array circuit package and the upper face of the printed circuit board and, in some embodiments, the standoffs may be comprised of circuit components. The printed circuit board may further include at least two alignment holes extending through the printed circuit board and located adjacent the ball grid array circuit package for receiving corresponding alignment pins of a probe array and aligning the probe array to make contact with the lower ends of the vias on the lower face of the printed circuit board. The probe array in turn includes a pin array of probe pins to provide electrical contact with the lower ends of the vias wherein each probe pin corresponds to and is co-located with a via of the via array to provide electrical contact with a ball pad of the ball grid array through the corresponding via of the via array.
In this respect, the present invention further includes a probe array for providing electrical contact with the ball pads of a ball grid array circuit package of a ball grid technology circuit assembly. In this aspect of the present invention, the ball grid array circuit assembly and the probe array include, in the ball grid array circuit assembly, a ball grid array circuit package containing integrated circuits and having, on a mounting face of the ball grid array circuit package, a ball grid array of ball pads forming electrical connections to the integrated circuits in the ball grid array circuit package. A printed circuit board is used for mounting the ball grid array circuit package and providing electrical connections to the ball pads of the ball grid array circuit package wherein the ball grid array circuit package is mounted to the printed circuit board with the mounting face of the ball grid array circuit package mating with an upper face of the printed circuit board. As described, the printed circuit board includes a via array of vias wherein each via extends from the upper face of the printed circuit board to a lower face of the printed circuit board, each via corresponds to and is co-located with a ball pad of the ball grid array, and each via contacts the corresponding ball pad of the ball grid array to provide a conductive path between the corresponding ball pad and the lower end of the via at the lower face of the printed circuit board to provide electrical access to the corresponding ball pad of the ball grid array of the a ball grid array circuit package. The probe array, in turn, includes a probe block containing the pin array of probe pins to provide electrical contact with the lower ends of the vias wherein each probe pin corresponds to and is co-located with a via of the via array to provide electrical contact with a ball pad of the ball grid array through the corresponding via of the via array. A probe attachment mechanism may be provided and includes a support frame enclosing the ball grid array circuit package, at least two shaft shaped fasteners mounted to the probe block adjacent to the pin array and extending through corresponding attachment openings through the printed circuit board to engage with the support frame to align the probe pins of the pin array with the vias of the via array and to secure the probe block to the ball grid array technology circuit assembly to make electrical contact between the probe pins and the lower ends of the corresponding vias on the lower face of the printed circuit board, and at least two alignment pins extending through corresponding alignment openings in the printed circuit board adjacent the ball grid array circuit package for aligning the probe pins of the probe array and the vias of the via array.